Publications

Journals

  1. U. Banerjee, A. P. Chandrakasan, “A Low-Power BLS12-381 Pairing Crypto-Processor for Internet-of-Things Security Applications,” IEEE Solid-State Circuits Letters, October 2021. [link] [arXiv]
  2. S. Maji, U. Banerjee, A. P. Chandrakasan, “Leaky Nets: Recovering Embedded Neural Network Models and Inputs through Simple Power and Timing Side-Channels - Attacks and Defenses,” IEEE Internet of Things Journal, August 2021. [link] [arXiv]
  3. R. T. Yazicigil, P. M. Nadeau, D. Richman, C. Juvekar, S. Maji, U. Banerjee, S. H. Fuller, M. R. Abdelhamid, N. Desai, M. I. Ibrahim, M. I. W. Khan, W. Jung, R. Han, A. P. Chandrakasan, “Beyond Crypto: Physical-Layer Security for Internet of Things Devices,” IEEE Solid-State Circuits Magazine, November 2020. [link]
  4. U. Banerjee, T. S. Ukyab, A. P. Chandrakasan, “Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols,” IACR Transactions on Cryptographic Hardware and Embedded Systems, August 2019. [link] [arXiv]
  5. U. Banerjee, A. Wright, C. Juvekar, M. Waller, Arvind, A. P. Chandrakasan, “An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications,” IEEE Journal of Solid-State Circuits, May 2019. [link] [arXiv]
  6. P. Mukhopadhyay, U. Banerjee, A. Bag, S. Ghosh, D. Biswas, “Influence of Growth Morphology on Electrical and Thermal Modeling of AlGaN/GaN HEMT on Sapphire and Silicon,” Solid-State Electronics, February 2015. [link]
  7. P. Mukhopadhyay, A. Bag, U. Gomes, U. Banerjee, S. Ghosh, S. Kabi, E. Y. I. Chang, A. Dabiran, P. Chow, D. Biswas, “Comparative DC Characteristic Analysis of AlGaN/GaN HEMTs Grown on Si(111) and Sapphire Substrates by MBE,” IEEE/TMS Journal of Electronic Materials, April 2014. [link]

Conferences

  1. M. R. Abdelhamid, U. Ha, U. Banerjee, F. Adib, A. P. Chandrakasan, “Wireless, Batteryless, and Secure Implantable System-on-a-Chip for 1.37mmHg Strain Sensing with Bandwidth Reconfigurability for Cross-Tissue Adaptation,” IEEE Custom Integrated Circuits Conference (CICC), April 2022. [link]
  2. S. Maji, U. Banerjee, S. H. Fuller, A. P. Chandrakasan, “A Threshold Implementation-Based Neural Network Accelerator Securing Model Parameters and Inputs Against Power Side-Channel Attacks,” IEEE International Solid-State Circuits Conference (ISSCC), February 2022. [link]
  3. S. Maji, U. Banerjee, S. H. Fuller, R. T. Yazicigil, A. P. Chandrakasan, “Securing Embedded Medical Devices using Dual-Factor Authentication,” IEEE International Symposium on Computer-Based Medical Systems (CBMS), June 2021. [link]
  4. U. Banerjee, A. P. Chandrakasan, “A Low-Power Elliptic Curve Pairing Crypto-Processor for Secure Embedded Blockchain and Functional Encryption,” IEEE Custom Integrated Circuits Conference (CICC), April 2021. [link] [DSpace]
  5. U. Banerjee, S. Das, A. P. Chandrakasan, “Accelerating Post-Quantum Cryptography using an Energy-Efficient TLS Crypto-Processor,” IEEE International Symposium on Circuits and Systems (ISCAS), October 2020. [link] [DSpace]
  6. U. Banerjee, T. S. Ukyab, A. P. Chandrakasan, “A Low-Power Side-Channel-Secure Configurable Accelerator for Post-Quantum Lattice-Based Cryptography”, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) Design Contest, August 2020. [link]
  7. S. Maji, U. Banerjee, S. H. Fuller, M. R. Abdelhamid, P. M. Nadeau, R. T. Yazicigil, A. P. Chandrakasan, “A Low-Power Dual-Factor Authentication Unit for Security of Implantable Devices,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) Design Contest, August 2020. [link]
  8. U. Banerjee, A. P. Chandrakasan, “Efficient Post-Quantum TLS Handshakes using Identity-Based Key Exchange from Lattices,” IEEE International Conference on Communications (ICC), June 2020. [link] [DSpace]
  9. S. Maji, U. Banerjee, S. H. Fuller, M. R. Abdelhamid, P. M. Nadeau, R. T. Yazicigil, A. P. Chandrakasan, “A Low-Power Dual-Factor Authentication Unit for Secure Implantable Devices,” IEEE Custom Integrated Circuits Conference (CICC), March 2020. [link] [arXiv]
  10. U. Banerjee, T. S. Ukyab, A. P. Chandrakasan, “Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols,” IACR Conference on Cryptographic Hardware and Embedded Systems (CHES), August 2019. [link] [arXiv]
  11. U. Banerjee, A. Pathak, A. P. Chandrakasan, “An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things,” IEEE International Solid-State Circuits Conference (ISSCC), February 2019. [link] [arXiv]
  12. U. Banerjee, C. Juvekar, A. Wright, Arvind, A. P. Chandrakasan, “An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for End-to-End Security in IoT Applications,” IEEE International Solid-State Circuits Conference (ISSCC), February 2018. [link] [arXiv]
  13. U. Banerjee, C. Juvekar, S. H. Fuller, A. P. Chandrakasan, “eeDTLS: Energy-Efficient Datagram Transport Layer Security for the Internet of Things,” IEEE Global Communications Conference (GLOBECOM), December 2017. [link] [DSpace]

Patents

Manuscripts and Technical Reports

Theses